Variation Tolerant On-Chip Interconnects

High-speed and low-power repeater for VLSI interconnects
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It is for anyone concerned with the design of next generation, high-performance electronics systems.

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This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in subnm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

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7. Comparison of the Designed Interconnects

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Journal of Semiconductors. Semiconductor Integrated Circuits.

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